Abstract—The non-binary Low Density Parity Check (LDPC) codes over Galois Fields GF(q = 2p) have evolved from the binary LDPC codes that are today an industry standard for channel coding. The performance of short block length codes is significantly higher for non-binary LDPC, at the cost of increased decoding complexity. The efficient decoder hardware implementation is still a challenging task. Most of the recently proposed hardware realizations are ASIC-oriented as they employ multiplierless computation units. This article concerns a different decoder design approach that is specifically intended for an FPGA implementation. The reformulated mixed-domain FFT-BP decoding algorithm is applied that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA. In this article we concentrate on the important issue of the proper selection of the numeric precision employed. We present the partially parallel extension of the mixed-domain decoder that operates for the structured codes. Then we carefully analyze the finite precision effects on the decoding performance. By simulation and synthesis results we show that it is advantageous to segment the decoder dataflow into 3 parts with different precision. The provided results also facilitate the precision selection for maximum performance or for some performance-complexity tradeoff.
Index Terms—Error correcting codes, LDPC codes, Non-binary codes, Iterative decoder, Hardware decoder
Cite: Wojciech Sulek, "Message Quantization Scheme for Nonbinary LDPC Decoder FPGA Implementation," Journal of Communications, vol. 10, no. 1, pp. 86-92, 2015. Doi: 10.12720/jcm.10.1.86-92
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