Abstract—This paper presents a high throughput Application-Specific Instruction-set Processor (ASIP) for cryptographic hash functions. The processor is obtained via hardware/software co-design methodology and accelerates SHA (Secure Hash Algorithm) and MD5 hash functions. The proposed design occupies 0.28 mm2 (66 kgates) in 65 nm CMOS process including 4.5 KB single port memory and 52 kgates logic. The throughput of the proposed design reaches 15.8 Gb/s, 12.5 Gb/s, 12.2 Gb/s, and 19.9 Gb/s for MD5, SHA-1, SHA-512, and SHA3-512, respectively under the clock frequency of 1.0 GHz. The proposed design is evaluated with state-of-the-art VLSI designs, which reveals its high performance, low silicon cost, and full programmability.
Index Terms—ASIP, Secure Hash Algorithm, MD5, VLSI (very large scale integration)
Cite: Yuanhong Huo and Dake Liu, “A High-Throughput Processor for Cryptographic Hash Functions," Journal of Communications, vol. 11, no. 7, pp.702-709, 2016. Doi: 10.12720/jcm.11.7.702-709
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