Abstract—Power-consumption reduction, resource optimization and cost reduction are inevitable on geophysical instrument design. We propose a new method for serial data clock domain crossing (CDC) transmission to solve the resource utilization problem of data acquisition interface in geophysical instrument design, combining with the use of digital programmable logic chip FPGA/CPLD. This method changes the usage mode of several simple serial-to-parallel and parallel-to-serial converting registers in original design to convert the CDC serial data instead of the traditional FIFO transfer way, which saves FIFO chips or FIFO modules in programmable logic chip resources fundamentally and can realize the same function as traditional design mode. Through long time verification in practical engineering, the method we proposed can be proved to be with reliability, effectiveness and stable operation.

Index Terms—FPGA/CPLD, Sigma-Delta ADC, Geophysical Instruments, clock domain crossing (CDC), data acquisition, Serial bus, FIFO